The AI semiconductor race is broadening. Transistor innovation still matters – new materials, gate architectures, and device physics remain important. But the spotlight is widening to include how those transistors are organized, connected, and cooled. Today’s headlines capture that shift. Chip design itself is being redefined, but newer, more advanced designs won’t come without significant challenges. In the shorter term, IBM’s new mainframe accelerator brings AI increasingly into enterprise infrastructure, and data center partners like Schneider, Hitachi, and Carrier are racing to industrialize the so-called “AI factory.” Read more below.
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3D-IC forces a total rethink of chip design
A new roundtable discussion in Semiconductor Engineering highlights how 3D integrated circuits (3D-ICs) are fundamentally changing the way chips are designed and built. The panel argues that stacked, heterogeneous dies will make tasks like verification and timing closure far more complex. For example, if you stack two full-size dies, you’ll then have to verify cross-die interactions under many more corner cases. As such, simulation, emulation, and “digital twin” strategies will all need to evolve.
Unlike traditional 3D packaging, which stacks or places chips side-by-side in a shared package, true 3D-IC connects multiple active silicon layers vertically using advanced bonding methods. This drastically shortens the distance data must travel, boosting performance and cutting power use – which could both result in massive bandwidth gains between compute and memory. But it also forces chip designers, packaging engineers, and thermal specialists to work far more collaboratively, since electrical, mechanical, and thermal interactions now happen in three dimensions rather than one. These are serious challenges, and won’t be overcome overnight. Unless vendors, foundries, EDA tools, and system architects coordinate tightly, many of those performance gains may be lost in verification or thermal trade-offs.
IBM brings Spyre AI accelerator to z17, LinuxONE 5, and Power11
IBM is adding a custom AI accelerator, called Spyre, to its flagship mainframe and Power systems later this month. Each Spyre card packs 32 specialized AI cores and can scale up to dozens per system, allowing these enterprise platforms to handle AI inference (such as fraud detection or real-time analytics) directly on the hardware that already stores and processes critical data. The company’s latest OS updates also improve how these accelerators interact with cloud and database environments. In practical terms, Spyre acts as a low-power PCIe accelerator that expands on the AI capabilities already built into IBM’s Telum II processor. It’s designed to offload and speed up inference workloads – tasks like detecting anomalies in financial transactions or scoring risks in real time. Multiple cards can be added to scale performance, giving enterprises an in-house alternative to relying solely on external GPU clusters. Spyre will be available for IBM x17 and LinuxOne 5 systems on October 28, and for Power11 servers in early December.
By embedding AI acceleration directly into mainframes and Power servers, IBM is bringing machine learning closer to the data, reducing the need to ship information to the cloud for analysis. That means faster insights, stronger security, and lower operational costs for banks, insurers, and governments that rely on IBM systems. It’s also a signal of a broader trend of AI inference becoming a standard feature of every class of computer, and not something confined to data centers or heavy-duty GPUs.
AI Semiconductors: What you need to know
Dell says GenAI is finally turning a profit: Dell told investors it expects AI server sales to roughly double next year, rising from about $10 billion to $20 billion as enterprise demand shifts from experimental training clusters to large-scale inference deployments. The company says AI infrastructure is moving from hype to a sustainable business, signaling that OEMs are beginning to see real profits from the AI boom.
XMOS plans GenAI-driven design tools: XMOS CEO Mark Lippett told EE Times that it’s developing natural-language tools that let engineers describe DSP and AI workloads in plain English, which the software then maps automatically onto XMOS’s multicore chips. The goal is to make hardware design as intuitive as coding, cutting development time and opening advanced silicon to smaller teams and faster product cycles.
Hitachi and OpenAI partner on AIDC power infrastructure: Hitachi will supply power transmission, distribution, and cooling infrastructure for OpenAI’s expanding data center network. The move underscores how AI growth now depends as much on physical and electrical infrastructure as on chips or algorithms, bringing traditional industrial firms deeper into the AI ecosystem. It comes after two mammoth OpenAI deals (between NVIDIA and ARM) were announced – signaling continued rapid infrastructure buildout by the company.
Schneider and NVIDIA are working together on AI data center reference designs: Schneider Electric and NVIDIA have released new reference designs that integrate power, cooling, and IT systems for NVIDIA’s GB200 and NVL72 clusters. By standardizing how large AI data centers are built, the partnership could make deployments faster, cheaper, and more energy-efficient, which could be essential as demand for compute capacity continues to surge.
Carrier debuts ‘QuantumLeap’ cooling in APAC: At Data Centre World Asia, Carrier launched a hybrid liquid–air cooling platform with predictive controls tailored for high-density AI racks. The system targets Asia’s rapidly growing AI data center market, where power and heat management are becoming defining limits on expansion.