This week’s semiconductor developments highlight how AI’s hardware backbone is evolving from all sides, from high-bandwidth memory to cloud-scale infrastructure. Samsung’s unveiling of its next-generation HBM4 chips signals a renewed push to capture Nvidia’s future AI workloads, while Google’s expanded partnership with Anthropic underscores how control over compute resources is becoming a defining advantage.
Memory and networking are continuing to emerge as some of the most important strategic battlegrounds for next-gen AI hardware, even as major players refine their chip architectures and supply chains for efficiency and scale.
Read more below.
Christian de Looper
Editor
RCR Wireless News
Top Stories
Samsung unveils next-gen HBM4
At SEDEX 2025, Samsung publicly showcased its HBM4 memory for the first time, challenging competitors SK Hynix and Micron in the next phase of high-bandwidth memory development. The company confirmed that HBM4 will feature an all-new architecture with improvements in energy efficiency, thermal performance, and stacking reliability, aided by advanced 3D packaging and hybrid bonding techniques. Samsung also reiterated its plan to begin mass production in 2026, aligning with next-generation AI GPUs expected to enter qualification that same year.
Samsung is looking to reestablish itself as a key supplier to Nvidia, which has so far leaned heavily on SK hynix for HBM3E. Discussions are reportedly underway to supply HBM4 for Nvidia’s upcoming accelerators, as both companies prepare for an era where AI model performance is increasingly constrained by memory bandwidth. By bringing HBM4 into the public spotlight early, Samsung aims to signal manufacturing readiness and secure early design wins before the industry’s transition to next-gen memory fully takes shape.
Google will supply Anthropic with up to one million TPUs
Google has deepened its partnership with Anthropic in a deal that will provide the AI company with access to up to one million of Google’s Tensor Processing Units (TPUs), representing one of the largest cloud compute commitments to date. The expanded agreement builds on years of collaboration between the two firms and includes broader integration of Google Cloud services, positioning Anthropic to scale training and deployment of its Claude models on Google’s most advanced AI hardware.
For Google, the deal reinforces its strategy of leveraging custom silicon to compete in the AI infrastructure race. By anchoring major model developers to its TPU ecosystem, Google aims to differentiate its cloud platform through performance and efficiency rather than GPU availability alone. Google, however, also competes directly with Anthropic through its own Gemini AI models, creating a dynamic where the company is both a cloud provider and a rival in generative AI. In a blog post, Anthropic noted that it will continue its diversified approach to AI infrastructure, using Google, Nvidia, and Amazon hardware.
AI Semiconductors: What you need to know
Intel’s next-gen AI GPU will launch next year: Intel confirmed that it plans to launch its upcoming AI GPU platform in 2026, targeting data center inference and training workloads. The chip is codenamed Crescent Island, and will be built on Intel’s Xe3P microarchitecture. It will feature 160GB of LPDDR5X memory – a notably slower form of memory than the new HBM3E and HBM4 memory used in many current- and next-gen data center chips.
Nvidia & TSMC mark U.S. production milestone with Blackwell wafer: Nvidia and TSMC have produced the first wafer of the Blackwell GPU architecture at TSMC’s Arizona facility, signalling that Blackwell has entered volume production on U.S. soil. The achievement underlines a push to “on-shore” critical AI hardware manufacturing in the U.S., with the Arizona site expected to produce chips using 2nm, 3nm, and 4nm technologies.
Broadcom introduces Thor Ultra AI Ethernet NIC: Broadcom introduced its Tomahawk 6 “Davisson” switch, a 102.4 Tb/s co-packaged-optics platform, alongside the Thor Ultra 800 G Ethernet NIC built on the open Ultra Ethernet Consortium (UEC) spec. The new products aim to boost bandwidth and reduce latency for large AI clusters, positioning Ethernet as a scalable alternative to proprietary interconnects like InfiniBand.
Axelera debuts “Europa” AI chip: The Dutch chip-maker announced its new AIPU, called Europa, designed for both edge and enterprise inference use-cases. It delivers a peak performance of 214 TOPS at just 45 watts of power, is equipped with 64 GB memory and 128 MB on-chip L2 SRAM, and supports 25 GB/s (200 Gbps) bandwidth. The architecture claims 3–5× better performance efficiency compared with competing solutions in generative AI and vision inference.
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