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AMD’s 256-core flagship targets agentic AI workloads
In sum – what we know:
- First HPC chip on 2nm – AMD says Venice is the first high-performance computing product to reach volume production on TSMC’s 2nm-class N2 node.
- A major spec jump – Top Venice configurations scale to 256 cores per socket with 16-channel memory, ~1.6 TB/s of bandwidth, and a claimed ~70% performance uplift over 5th Gen Turin.
- Verano joins the lineup – A second 6th Gen EPYC line, Verano, uses a new SP8 socket with LPDDR integration and targets cloud scale-out and AI inference rather than peak HPC.
AMD has moved its 6th Gen EPYC “Venice” server CPUs into volume production, marking the transition from engineering samples and pilot runs into scaled manufacturing at TSMC’s 2nm fabs in Taiwan. The chips are built on AMD’s Zen 6 core architecture and TSMC’s N2 2nm-class node, with commercial deployment targeted for later this year.
What makes this notable beyond the usual roadmap checkpoint is positioning. AMD is calling Venice the first high-performance computing product to reach production ramp on a 2nm node, putting it ahead of rival data center CPUs at this process generation. The target customers are predictable — hyperscalers, cloud providers, and large enterprise — but the workload framing is more specific. AMD is tying Venice directly to “agentic AI,” the more autonomous, multi-stage systems that put sustained pressure on compute, memory bandwidth, and energy budgets in the data center.
Venice silicon and platform upgrades
The headline number is core count. Top-end Venice configurations scale up to 256 CPU cores per socket, doubling the 128-core ceiling that defines much of the current EPYC lineup and pushing well past the 192-core Turin SKUs. AMD claims roughly 70% higher compute performance compared to the 5th Gen EPYC “Turin” parts — though the company hasn’t fully detailed the workloads, configurations, or power envelopes behind that number, so it’s worth treating with the usual caution applied to vendor-supplied uplift figures.
To support all that silicon, AMD is introducing a physically larger SP7 socket with a higher power delivery envelope. Memory gets a substantial upgrade too, with support for up to 16 channels and around 1.6 TB/s of per-socket bandwidth — a meaningful jump aimed squarely at AI and HPC workloads that are increasingly bandwidth-bound rather than compute-bound. I/O scales accordingly, with reporting noting doubled CPU-to-GPU bandwidth, which strongly implies PCIe 6.0 or an equivalent high-speed interconnect. That last point matters in heterogeneous clusters, where EPYC CPUs coordinate, pre-process, and post-process data around GPU and accelerator nodes.
Verano and the wider 6th gen family
Venice isn’t the whole story. AMD has also disclosed “Verano” as a second, distinct 6th Gen EPYC line, also fabricated on TSMC 2nm. Where Venice is the flagship aimed at maximum throughput, Verano is optimized for performance-per-dollar-per-watt, targeting cloud scale-out and AI inference rather than peak HPC.
Verano will use a new SP8 socket — the successor to today’s SP6 — with more conventional power and thermal envelopes than SP7. It’s expected to feature first-class LPDDR integration, which makes sense for dense scale-out deployments where memory power and bandwidth-per-watt matter more than absolute capacity per node. Together, Venice and Verano signal that AMD plans to extend 2nm across its data center roadmap rather than treating Venice as a one-off flagship.
TSMC 2nm production and Arizona expansion
Volume production is ramping across five TSMC 2nm fabs in Taiwan. That’s a substantial footprint, and Venice gives TSMC something it arguably needs — a way to diversify 2nm demand beyond mobile and consumer SoCs. Apple has reportedly secured the lion’s share of initial N2 capacity for its own chips, but landing AMD as a lead HPC customer broadens the node’s commercial base. TSMC CEO C.C. Wei has publicly positioned AMD in exactly that role for 2nm at both the Taiwan and Arizona sites.
AMD says it plans to ramp Venice production at TSMC’s Arizona campus eventually, tied to Fab 21 Phase 3, which is slated for N2 and future A16 processes. But volume 2nm production in Arizona isn’t expected before around 2028. In practice, that means Venice’s entire initial commercial life will rely on Taiwan-based capacity, with U.S. production a medium-to-long-term plan that likely lines up with later refreshes or follow-on 2nm EPYC generations. AMD frames the Arizona expansion as part of a broader push for geographic resilience, which is a fair pitch — but it’s also one that doesn’t materially change near-term supply-chain exposure.
Conclusions
Being first to volume on a 2nm-class HPC CPU is a genuine milestone, but a few caveats deserve attention. Early N2 yields remain a variable, and Apple’s priority access to TSMC’s 2nm capacity could constrain how much supply AMD actually gets in the early window. Intel is pushing its own 18A (1.8nm-class) Xeon lines, including Clearwater Forest, but isn’t yet at equivalent 2nm-class volume for data center parts. And custom ARM silicon — AWS Graviton, Google Axion, Microsoft Cobalt — along with vendors like Ampere continues to actively erode x86 share in cloud segments, which is part of what Venice and Verano are designed to defend against.
Several technical specifications also remain undisclosed, including exact TDP ranges, cache configurations, full platform features like PCIe and CXL lane counts, and precise launch dates for individual SKUs. AMD has the broad shape of the generation in public view, but the details that will actually determine how Venice and Verano land in customer hands are still to come.
