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Leading-edge chip prices face annual hikes through 2029 as AI demand surges

In sum – what we know:

• Two foundries, two strategies – TSMC is applying broad 3–10% increases across its advanced portfolio, while Samsung is imposing steeper 10–15% hikes on a narrower slice of 5 nm and 4 nm capacity.
• 2 nm as a permanent premium – TSMC’s first-gen 2 nm wafers debut around $30,000 — a 50% jump over 3 nm framed as a permanently higher floor — while Samsung plans to undercut at roughly $20,000–25,000.
• The bill lands downstream – Nvidia, AMD, Apple, Qualcomm, and MediaTek absorb the wafer hikes as margin compression or higher device prices, with smaller fabless players the most exposed.

If you were hoping chip prices had finally stabilized, 2026 has other plans. TSMC and Samsung Foundry — the only two companies capable of manufacturing the world’s most advanced chips at scale — are both raising prices on their leading-edge nodes. TSMC is applying broad increases of 3–10% across its advanced portfolio, while Samsung is taking a more surgical approach, imposing hikes of roughly 10–15% on its 5 nm and 4 nm-class wafers.

The downstream effects are fairly predictable. GPUs, AI accelerators, and premium smartphone SoCs all live on these nodes, and the companies designing them — Nvidia, AMD, Apple, Qualcomm, and the rest — will be absorbing higher wafer costs across their next several product generations. Some of that will get eaten as margin compression. A good chunk of it probably won’t.

It’s also worth noting that these hikes aren’t happening in isolation. They’re part of a broader 2026 repricing cycle sweeping through the semiconductor supply chain, with foundry, memory, and packaging costs all rising at once. In other words, the most expensive part of your next device is getting more expensive from multiple directions simultaneously.

Timeline of the price hikes

The groundwork was laid in late 2025, when TSMC reportedly told customers to expect annual price increases on advanced nodes starting in 2026 and continuing through 2029. Samsung followed with its own notices in the fourth quarter of 2025, targeting its mainstream 5/4 nm processes as AI-related orders surged.

By early 2026, TSMC’s 3–10% increases for sub-7 nm nodes were confirmed, establishing a new baseline for 3 nm and everything below it. Samsung, meanwhile, was preparing roughly 10% hikes for certain 4 nm and 8 nm lines by February. The pressure didn’t stay confined to the leading edge, either. By March, European, U.S., and mature-node foundries were implementing their own price rises effective April 1, pushing the cost burden further downstream.

The mid-2026 numbers tell the clearest story. TSMC’s 3 nm wafers moved from about $20,000 to $21,000–22,000, and its first-generation 2 nm wafers are expected to debut around $30,000. Samsung’s initial 2 nm pricing, by contrast, is estimated in the $20,000 range — a meaningful gap. The broader contrast holds throughout the timeline. TSMC set out its structured annual roadmap in late 2025 and stuck to it, while Samsung issued narrower, targeted increase notices in waves through early 2026.

TSMC’s pricing

TSMC’s adjustments cover its entire advanced portfolio — generally defined as 7 nm and below — with the heaviest emphasis on 5 nm, 3 nm, and the upcoming 2 nm node. The 3 nm increase works out to roughly 5–10%, landing wafers at approximately $21,000–22,000 each.

The 2 nm tier is a different animal. At around $30,000 per wafer, it carries a 50% premium over 3 nm, and analysts are careful to frame it not as a hike but as a permanently higher starting point. That distinction matters. The shift to gate-all-around transistors and the sheer number of EUV layers involved mean 2 nm chips will simply cost more to make, indefinitely. There’s no cheaper version coming.

Layer the annual 3–10% increases on top — baked in through at least 2029 — and TSMC has effectively told the industry that leading-edge silicon gets more expensive every year for the rest of the decade. The strategy behind it is straightforward enough. Higher baseline pricing lets TSMC prioritize customers willing to pay premium rates, and it funds the enormous capital expenditures required for new fabs in the U.S., Europe, and Asia. Notably, mature nodes at 28 nm and older have seen little or no significant increase so far, which tells you where TSMC believes its pricing power actually lives.

Samsung Foundry’s pricing

Samsung has gone the other direction. Rather than raising prices everywhere, it’s concentrating on the nodes where demand is strongest — the AI-critical 5 nm and 4 nm processes, which are seeing hikes of 10–15%. That’s steeper than anything TSMC is doing on a percentage basis, just applied to a much narrower slice of the portfolio. Roughly 10% increases are also planned for some 4 nm and 8 nm lines serving mobile, consumer, and SoC customers, however it seems as though the price hike will only apply to new customers, not existing ones.

The logic is opportunistic, and frankly, hard to argue with. Samsung’s 5/4 nm capacity has seen a significant rise in orders for AI applications, giving it leverage it hasn’t had in years. Raising prices while still filling the fabs is exactly what you’d expect a foundry in that position to do.

The more interesting move is what Samsung isn’t raising. Its upcoming 2 nm pricing is expected to sit well below TSMC’s — that estimated $22,000–25,000 range against TSMC’s $30,000. The apparent plan is to charge aggressively where its capacity is booked and undercut where it needs to win strategic design contracts at the bleeding edge. Combined with surging memory prices and a favorable shift toward high-value products, the hikes are expected to meaningfully improve Samsung’s overall profitability — something its foundry business has needed for a while.

Key drivers behind the price hikes

The simplest explanation is that demand has outrun supply, and not by a little. AI accelerators, GPUs, and high-performance computing chips have consumed essentially all available capacity at 5/4 nm, 3 nm, and the future 2 nm nodes, with orders reportedly stretching through at least 2027.

And the AI boom doesn’t stop at logic. Expanding compute requirements cascade into packaging, HBM memory, and interface chips, driving systemic cost increases across the whole stack. A wafer price hike is one line item in a much larger inflation story.

The cost side is just as real, though. New fabs in the U.S. and Europe face vastly higher construction, labor, and regulatory compliance costs than the legacy facilities in Asia they’re meant to complement. EUV lithography keeps getting more complex, and the move to gate-all-around transistors at 2 nm dramatically inflates tool counts and per-wafer costs. Add general inflation in materials, energy, and specialized equipment, and the foundries have a legitimate case that their own costs are climbing — even if the fully booked order books suggest they’d have pricing power regardless.

It’s worth noting that neither company escapes these pressures. TSMC and Samsung face essentially identical macroeconomic headwinds from advanced EUV implementation, and government subsidies in the U.S. and Europe soften the capital blow without neutralizing it. The subsidies help build the fabs. They don’t make the wafers cheap.

No relief any time soon

For the big fabless designers, like Nvidia, AMD, Apple, Qualcomm, and MediaTek, the 3–10% base wafer hikes flow directly into their cost structures. Next-generation flagship GPUs and premium smartphone SoCs will either launch at higher prices or squeeze margins somewhere in the chain, and probably some of both. Designers on Samsung’s 5/4 nm lines aren’t insulated either; they’re facing similar cost shocks to those booked on TSMC’s fully loaded capacity, just via steeper percentages on fewer nodes.

Hyperscalers face their own version of the problem. Ballooning capital expenditures for AI infrastructure could eventually push up the pricing of consumer and enterprise cloud AI services. And smaller fabless companies are the most exposed of all, facing full list-price hikes and capacity constraints that the giants can negotiate around. That dynamic tends to accelerate consolidation, and there’s little reason to think this cycle will be different. Meanwhile, the geopolitically motivated push toward regionalized chip production carries its own bill, and those elevated operating costs inevitably land in end-product prices.

That said, there’s plenty here that remains genuinely uncertain. Exact foundry rates are confidential and vary drastically by customer volume, existing relationships, and product mix — the reported percentages are industry estimates, not published rate cards. Reports don’t even agree on what counts as an “advanced node,” which makes standardized cost tracking across sources effectively impossible. And, the durability of these prices is untested. If demand collapses cyclically, or if new capacity ramps faster than planned, today’s pricing power could erode quickly — though TSMC’s multi-year guidance suggests it’s betting demand stays ahead of supply for years.

How much of this reaches consumers is also contested. Device makers and cloud providers will absorb some of it through margin compression and hardware optimization, and pass the rest along. The split is anyone’s guess. Perhaps the most interesting open question is Samsung’s posture at 2 nm. It can hold its deep discount against TSMC to win share, or close the gap and chase profitability once its yields improve — but it probably can’t do both. How that plays out will shape leading-edge pricing for the rest of the decade.