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Cognichip just got $60 million in Series A funding to bring its concept to life
In sum – what we know:
- A massive funding injection – Cognichip closed an oversubscribed $60 million Series A led by Seligman Ventures, bringing its total capital to $93 million.
- Physics-informed foundation model – The company’s Artificial Chip Intelligence (ACI) platform combines AI with physics-based reasoning to optimize RTL descriptions, netlists, and circuits.
- Disrupting design timelines – The startup claims its technology can reduce chip design costs by 75% and accelerate completion by 50%, aiming to compress multi-year development cycles.
There’s a ton of hype around AI chips, but what about AI-designed chips. That’s the idea behind Cognichip, which is building what it describes as the first physics-informed AI foundation model for semiconductor design — and it just closed a $60 million Series A led by Seligman Ventures. The round was oversubscribed, announced April 1, 2026, and brings total funding to $93 million since the company was founded in 2024. That earlier $33 million seed round had backing from Lux Capital, Mayfield, FPV, and Candou Ventures.
The money is interesting, but the names attached are pretty interesting too. Intel CEO Lip-Bu Tan and Seligman Ventures managing partner Umesh Padval have both taken board seats. CEO Faraj Aalaei and Chief Product Officer Stelios Diamantidis lead the company, both with deep roots in semiconductors and AI. Cognichip came out of stealth in May 2025 and has been moving fast to plant itself right at the intersection of two absurdly capital-intensive worlds — AI and chip design.
What is Artificial Chip Intelligence?
The central idea behind Cognichip is something it calls Artificial Chip Intelligence, or ACI — pitched as the world’s first physics-informed foundation model purpose-built for semiconductors. The distinction the company draws is that ACI isn’t just general-purpose AI thrown at chip design problems. It weaves together AI with physics-based reasoning to automate and optimize across multiple stages of the design process.
In more concrete terms, the model trains on RTL (Register Transfer Level) descriptions, post-synthesis netlists, circuits, and specifications — giving it the ability to operate across different design environments rather than being locked into one narrow task. Cognichip describes the system as a unified platform that combines datasets, models, and infrastructure, working conversationally and securely alongside engineers. Less “replace the human” and more “deeply technical co-pilot.”
The company says ACI runs at very high speeds with high parallelism, which matters a lot when you consider that traditional chip design workflows are sequential and heavily manual. If those claims pan out, the practical shift would be engineers moving from hands-on technical execution to higher-level architectural decisions. That’s a big “if,” though.
Training and technical approach
Under the hood, ACI is built on a proprietary dataset that Cognichip says it’s been developing for two years. The dataset blends synthetic data with licensed data from industry partners. One of the more compelling technical claims is that Cognichip has built specialized procedures letting chipmakers train the model on their own proprietary data without ever exposing it to outside parties. When proprietary data isn’t available, the system falls back on open-source alternatives.
For real-world validation, Cognichip points to a demonstration at San Jose State University where students used the model to design RISC-V-based CPUs. That’s an encouraging signal for usability and accessibility, though designing a student CPU is a far cry from proving the system can wrangle a modern data center GPU with tens of billions of transistors. It does, however, hint at a broader ambition of making chip design reachable beyond the traditional pool of deep-domain experts.
Performance
The problem Cognichip is going after is enormous. Advanced chip designs currently take three to five years from conception to mass production, with the design phase alone sometimes eating up to two years before physical layout even starts. For context on the complexity involved, Nvidia’s Blackwell GPU packs 104 billion transistors requiring extraordinarily intricate coordination. Entire markets can shift in the time it takes to design and fabricate a cutting-edge chip, potentially making the whole investment less relevant by the time silicon actually ships.
Against that backdrop, the performance claims are bold. Cognichip says ACI can cut chip design costs by up to 75% and speed up completion by up to 50%, potentially compressing design cycles significantly. The company also claims improvements in first-pass silicon success rates, meaning chips are more likely to work correctly on the first manufacturing attempt, which is hugely valuable when respins can cost millions. On top of that, the system targets reductions in excessive chip size and power consumption, both of which directly hit manufacturing cost and energy efficiency.
These numbers are striking, but they deserve skepticism. “Up to” claims in any industry should be taken with a grain of salt, and semiconductor design involves so many variables that generalized performance numbers are hard to map onto specific real-world cases. That said, even modest improvements in design timelines and first-pass success rates represent massive value.
Where to go from here
Cognichip says it’s currently working with more than 30 global semiconductor companies, including several among the top 20 by revenue. The platform plugs into digital, analog, mixed-signal, and foundry environments, suggesting broad applicability across different chip types and manufacturing contexts. The company reports measurable improvements in early customers’ production workflows, though no specific metrics or case studies have been made public.
One of Cognichip’s bigger stated ambitions is to democratize chip design, opening it up to innovators who lack the deep semiconductor expertise or massive budgets traditionally needed to take a chip from concept to silicon. The San Jose State demo is a small proof point in that direction, but the real test will be whether non-expert teams can use the platform to produce designs that genuinely compete with what established semiconductor firms put out.
The larger question hanging over all of this is whether an industry that’s relied on a relatively stable set of EDA tools and workflows for decades is actually ready to embrace a fundamentally AI-driven approach. The funding and Lip-Bu Tan’s board-level endorsement suggest at least parts of the industry are willing to make that bet. But the distance between investor enthusiasm and production-grade adoption in semiconductor design is vast, and Cognichip will need to prove its claims at scale with paying customers before the revolution it’s promising starts looking like anything close to reality.
