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Reported AMD tie-up pairs Google TPU matrix engines with x86 CPU cores
In sum – what we know:
- A hybrid TPU v10 – Google is reportedly working with AMD on a 10th-generation TPU that puts x86 CPU cores directly on the accelerator package.
- The RL angle – On-package CPUs shorten data paths for reinforcement learning, robotics, and agentic workloads that lean heavily on control logic.
- A big AMD win – The deal would put custom x86 IP and packaging from AMD into Google silicon and open follow-on hyperscaler opportunities.
Google has settled into a pretty quick cadence when it comes to refreshing its TPUs, but its next refresh might see it bring a new partner on board. According to a client note from SemiAnalysis, Google is reportedly working with AMD on a project tied to its 10th-generation Tensor Processing Unit — a hybrid AI ASIC that would put general-purpose CPU cores directly on the accelerator package, rather than leaving them on a separate board a PCIe hop away.
The TPU v10 family — associated in some analytical notes with the internal codename “Ice Fish” — may also include distinct training (v10t) and inference (v10i) variants alongside this new CPU-heavy chip. It’s the last one where AMD would apparently come in.
Technical details
The rumored chip would pair Google’s proprietary TPU matrix-multiplication engines with on-package CPU cores, most likely built on AMD’s x86 Zen IP. The target, per SemiAnalysis, is workloads like reinforcement learning, robotics, and agentic AI systems that involve environment simulation, complex branching, and constant back-and-forth between decision logic and numeric computation.
Standard generative AI workloads are overwhelmingly matrix-heavy, which is exactly what TPUs were built for. RL is a little different though. It leans on CPUs far more, and in today’s architectures those CPUs sit on the other side of a PCIe or similar board-level connection, which adds latency and burns power moving data back and forth. Putting the control logic on the same package as the matrix engine shortens those data paths, allows finer-grained coordination between the two, and could make multi-step RL training loops meaningfully more efficient.
Nvidia has been heading in the same direction for a while — Grace Hopper already pairs a CPU and GPU in a tightly coupled design. As such, a hybrid TPU would be Google joining an industry shift rather than starting one. But compared to previous TPU generations, it would still mark a real change in philosophy. A v10-era chip with integrated x86 cores would be closer to a heterogeneous, programmable compute module.
Partner ecosystem
If AMD is involved, it’s probably not designing the TPU itself. According to the report, AMD’s likely contribution is CPU core IP, advanced packaging, and 3D integration technologies like SoIC — not a takeover of the matrix engine work. That work still belongs to Google and Broadcom, which signed a “long-term” co-design agreement in April reportedly covering TPU generations v8 through v11. Broadcom remains the core partner for accelerator logic and networking regardless of what AMD ends up doing.
Why AMD rather than Intel? The argument is fairly straightforward. AMD has publicized custom silicon teams willing to build bespoke chips for hyperscalers, and it has real experience fusing CPUs and GPUs into sophisticated data center APUs. Intel, by contrast, has less demonstrated track record in exactly this kind of hybrid x86-plus-accelerator design. Whether that reasoning is Google’s or just the analysts’ is impossible to say.
The AMD chatter also fits a broader pattern. Google is reportedly exploring Samsung Foundry alongside TSMC for parts of the v10 generation and is said to be in talks with Marvell for other custom AI chips. Taken together, it looks like a deliberate effort to spread the AI hardware supply chain across multiple foundries and multiple silicon partners rather than concentrating risk in any one of them.
AMD’s big win
If the rumor pans out, this would be a big win for AMD. AMD already competes with Nvidia on general-purpose accelerators through its Instinct line, but a Google TPU engagement would put it in a different category entirely, and could plausibly open the door to follow-on custom work with other hyperscalers eyeing similar hybrid designs.
For Google, the appeal is vertical integration. A hybrid TPU would let it build platforms tuned for its own RL and agentic workloads, and potentially offer Google Cloud instances where the accelerator natively handles both numeric computation and control-plane logic — something the GPU-centric competition can’t easily match today. It also reduces Google’s exposure to Nvidia’s ecosystem, which is a hedge every hyperscaler is currently pursuing in one form or another.
