Table of Contents
Lab validation advances the low-power memory architecture, but yields and customers remain uncertain
In sum – what to know:
- HBC puts compute at the base – The architecture places an active die beneath commodity LPDDR memory rather than using conventional high-bandwidth memory, reducing selected data journeys from millimeters to micrometers.
- Early silicon, not production – The validated test vehicle used a two-layer memory stack rather than the four-layer configuration intended for production, and no measured bandwidth, power or yield data accompanied the announcement.
- Key uncertainties ahead – Manufacturing yield on four-layer stacks, final pricing amid LPDDR cost inflation, and customer volume commitments are all unproven before the AI250 is scheduled to sample in H1 2027.
Qualcomm has announced that its first-generation High Bandwidth Compute silicon has completed hardware validation in its San Diego lab. HBC is the memory architecture underneath the Dragonfly AI250 inference accelerator, which Qualcomm now expects to sample in the first half of 2027.
The announcement came in a blog post by Rashid Attar, senior vice president of engineering at Qualcomm Technologies. Currently, there’s no shipping HBC hardware, HBC-based customer silicon, independent performance measurement, pricing or volume shipment date. Qualcomm also told reporters it tested an early two-layer memory stack rather than the four-layer configuration intended for production.
For Qualcomm, working silicon offers something more concrete than another roadmap commitment. It still has to turn that silicon into a manufacturable, competitively priced rack-scale system. The timing aligns with broader memory-cost inflation across the AI accelerator supply chain.
What Qualcomm actually validated
Engineers used industry-standard automated test equipment, the lab systems that drive signals through a chip and check its responses, to exercise production-representative data pathways. The tests covered the full memory read-write path and computations performed near the memory, using randomized weights and activations at production-representative dimensions. Weights are the parameters that make up an AI model, while activations are the intermediate values produced as that model processes data.
Qualcomm told reporters the test vehicle combined two layers of DRAM, the working memory used to hold that data, with a compute die underneath. Production HBC stacks are expected to use four DRAM layers. Qualcomm hasn’t disclosed a four-layer bandwidth measurement, power figure or yield, so the validation establishes the basic operation of the architecture rather than the behavior of a finished memory stack.
Wafer-to-wafer bonding was also developed and characterized with foundry and assembly partners across multiple technology generations. That process joins entire wafers before the individual dies are separated, requiring extremely precise alignment. Qualcomm says it has built redundancy and remapping into the design so defective memory locations can be detected and bypassed, and that its testing exercised electrical, thermal, bonding and interface failure modes.
A data center product’s design has been sent to manufacturing too. Qualcomm didn’t identify which product. It also says early bring-up of a logic base with bonded DRAM tiers is “yielding today”, but that statement shouldn’t be confused with a disclosed production yield rate. No absolute bandwidth, stack yield, bond pitch, clock rate or power consumption accompanied the announcement.
The architectural distinction is more informative than the lab checklist. Conventional high-bandwidth memory, or HBM, places DRAM dies on a base die that has historically handled only interface and test functions, and connects the stack to a separate processor over a very wide interface. HBC puts an active compute die at the bottom of the stack and bonds commodity LPDDR memory directly above it. LPDDR is the low-power memory commonly used in phones and PCs, rather than the specialized DRAM developed for HBM.
Vertical connections called through-silicon vias, or TSVs, carry data through the stack. Qualcomm’s approach reduces selected data journeys from millimeters to micrometers and makes bandwidth heavily dependent on the density of the bonds rather than the number of external pins.
That base die isn’t a full processor. It handles bandwidth-intensive portions of inference close to the data, particularly decode work. Decode is the token-generation stage that repeatedly reads model information as an AI system produces its response. Compact results then travel back to the main AI250 accelerator over a comparatively slower link.
This is also Qualcomm’s answer to custom HBM, which places more sophisticated logic beneath an HBM stack. Qualcomm argues that custom HBM still sends the data out to the main processor, while HBC performs selected operations where the data resides. The real distinction is therefore how much work happens inside the memory complex, not simply whether there’s logic underneath the DRAM.
Reducing the traffic between the memory stack and main accelerator has packaging implications. Qualcomm says HBC products can use standard 2D organic substrates rather than the silicon interposers or bridges used by advanced packaging technologies such as TSMC’s CoWoS and Intel’s EMIB. Those technologies help processors communicate with HBM, but they add cost and depend on manufacturing capacity that has constrained AI accelerator supply.
Tony Pialis, executive vice president and general manager of Qualcomm’s data center business, said at Investor Day that with this approach, “congestion that you saw with HBM is gone.” Removing the interposer would eliminate one significant packaging bottleneck. It wouldn’t eliminate TSV stacking, wafer bonding or the need to secure DRAM supply, and Qualcomm still has to demonstrate that its process yields at production scale.
The 18x claim
Qualcomm’s headline claim is 18x the effective memory bandwidth of external LPDDR5X, the memory configuration used by its AI200 accelerator. The comparison is against LPDDR5X, not DDR5, and it measures HBC against Qualcomm’s own preceding architecture. It doesn’t establish an 18x advantage over an HBM-equipped Nvidia or AMD system.
The 18x is a relative gain Qualcomm says it measured on its early test silicon. By contrast, the frequently repeated 133TB/s figure for an AI250 card is an absolute design target carried over from June 2026, not a measured result from the validated silicon. And “effective memory bandwidth” is Qualcomm’s own term for bandwidth available to computations inside the memory stack.
That isn’t the same currency as the HBM figures published by Nvidia and AMD. Nvidia’s Vera Rubin GPU pairs 288GB of HBM4 with 19.2TB/s of bandwidth, while AMD’s MI455X specifies 432GB of HBM4 and 23.3TB/s. Those figures describe data crossing the package interface between memory and processor. Qualcomm’s figure describes bandwidth available where its near-memory computation occurs. Putting 133TB/s beside 19.2TB/s without that explanation would produce a comparison that looks precise and means very little.
Qualcomm now claims more than 5x the bandwidth per watt of published HBM4 specifications. At Investor Day, it targeted 6x against HBM more generally. That isn’t necessarily evidence of a silicon regression, because the comparison basis changed along with the number. It does mean the June and November claims aren’t interchangeable.
Qualcomm’s own footnote describes its figures as “estimates based on measured first-generation Qualcomm HBC silicon results normalized to target operating conditions and compared with published competing product specifications.” Final performance, it adds, may vary with the product, workload and system configuration. In practical terms, Qualcomm measured early silicon, adjusted those results to its intended operating conditions and compared the extrapolation with competitors’ specifications. It didn’t run finished products side by side under identical conditions.
Gerardo Giaretta, Qualcomm’s vice president and general manager for data center CPU and AI, says the energy spent moving data is “at least one order of magnitude less” with HBC. That claim concerns data movement specifically. It doesn’t demonstrate a tenfold reduction in energy use for a complete accelerator, server or rack.
Nor is there independent or customer-measured tokens-per-watt data yet. That omission matters because tokens per watt, the number of model output units produced for a given amount of energy, is the metric Qualcomm itself presents as the relevant measure of inference efficiency.
Competitors are attacking the same decode bottleneck with different architectures. Intel’s GPU D270, formerly code-named Crescent Island, is a 350W air-cooled PCIe card with 160GB of LPDDR5X on Intel’s own card and up to 480GB on partner-built cards, so it also avoids HBM. It doesn’t put Qualcomm-style near-memory compute underneath the DRAM. Nvidia, meanwhile, pairs Rubin with Groq 3 LPX systems for memory-intensive decode work. An LPX rack combines 256 language processing units with 128GB of SRAM, a very fast form of on-chip memory, and carries a quoted 40PB/s of SRAM bandwidth per rack. That number reflects yet another architecture and measurement boundary.
From lab to rack
The AI250 is Qualcomm’s second-generation rack-scale inference platform and the first product scheduled to integrate HBC Gen 1. Its published configuration includes 768GB of memory per card and 56 cards per rack, producing 43TB of rack memory and an aggregate 7.455PB/s of effective bandwidth.
The rack is specified at 140kW of thermal design power, meaning the cooling system is designed around that heat load. It uses the Open Compute Project’s ORv3 single-wide rack format with a cableless backplane and supports air or direct liquid cooling. PCIe 6.0 provides scale-up connections within the system, while Ethernet with RoCE handles scale-out connections across systems. RoCE is a networking method that enables low-latency data transfers over Ethernet.
Qualcomm says the platform will support models with up to 10 trillion parameters and context lengths of up to 1 million tokens. Context length is the amount of input and preceding output a model can consider at once. These are deployment targets, however, not results demonstrated on the validated HBC stack.
Even the rack specifications have moved between Qualcomm materials. Several Nov. 2 reports carried 38.6TB of memory and 7.4PB/s of effective bandwidth from the June information, while the October 2025 launch materials cited 160kW of rack power. Qualcomm’s live product page now lists 43TB, 7.455PB/s and 140kW, although its AI-accelerators page still lists 38.6TB and 7.4PB/s. The product page is the better reference, but all of the rack-level figures should be treated as provisional until Qualcomm publishes final system documentation.
Its performance claims remain estimates too. Qualcomm projects 4x–8x better bandwidth per watt per card than contemporary GPU architectures and up to 8x better tokens per second per watt during decode for select models. Neither claim has been independently tested, and the HBC contribution can’t yet be separated from the performance of the complete AI250 accelerator, its cooling configuration or Qualcomm’s software stack.
Manufacturing yield is the biggest hardware unknown. Defects become harder to avoid as stacks grow, and one bad DRAM layer can condemn an otherwise functional assembly. Redundancy and remapping can recover some defective areas, but Qualcomm hasn’t shown that those mechanisms can deliver commercially viable yields on four-layer stacks at production dimensions. Successful bonding across earlier test vehicles doesn’t answer that question.
The economics of commodity LPDDR have also become less comfortable. TrendForce estimated LPDDR5X contract prices would rise 78–83% quarter on quarter in Q2 2026, and Counterpoint put Q3 2026 DRAM revenue growth at 369% year on year, driven mainly by price, with bit shipments up only about 4%. Those figures describe an extreme memory cycle rather than a reliable long-term cost baseline. Still, they weaken any assumption that LPDDR will remain cheap and readily available simply because it isn’t HBM.
Samsung and SK hynix are collaborating with Qualcomm on HBC commercialization while continuing their own HBM roadmaps. Micron and SK hynix also appeared on Qualcomm’s June Dragonfly ecosystem partner list, but Qualcomm hasn’t named the production LPDDR supplier for HBC. If the architecture scales, it will create another source of demand for LPDDR wafers and place Qualcomm in allocation discussions alongside phone, PC and server buyers.
Qualcomm says Microsoft will deploy HBC in the AI250 and AI300, which would be the strongest public endorsement of the architecture. The claim comes from Qualcomm, which introduced Microsoft at its June 24 Investor Day with a pre-recorded message from Satya Nadella. It hasn’t attached a volume, deployment date or workload to that statement, though. Meta’s named commitment concerns Qualcomm’s C1000 CPU, while Amazon’s involves custom silicon. HUMAIN announced a target of 200MW of AI200 and AI250 racks in Saudi Arabia in October 2025, eight months before HBC was unveiled, without splitting it between the two, and no customer has publicly committed to HBC-based accelerators in volume since.
The roadmap adds timing pressure. AI200 carries Qualcomm’s 2026 commercial data center ramp. AI300 is scheduled to sample in 2028 with HBC Gen 2, a targeted 54x effective-bandwidth increase over AI200 and support for UALink, an open standard for connecting accelerators within larger systems. The C1000 CPU, with more than 250 Oryon cores, is also slated for 2028.
AI250 samples in the first half of 2027 would likely leave customer qualification running through that year, making volume in 2028 plausible. By then, Nvidia’s Rubin generation should be late in its lifecycle, with Rubin Ultra due in 2027 and Feynman in 2028, while AMD’s MI400 and Helios rollout should be established. Qualcomm’s own AI300 could also narrow the AI250’s commercial window, particularly if customers prefer to qualify the higher-bandwidth platform.
Qualcomm is targeting $5 billion of data center revenue in fiscal 2027 and $15 billion by fiscal 2029, a projection driven by aggressive AI infrastructure expansion. Those targets cover custom silicon, AI200 systems, CPUs and other products, so they can’t be treated as an AI250 order book. Management has also said supply, rather than demand, is the constraint on fiscal 2027 upside. HBC could ease one packaging constraint while leaving Qualcomm exposed to memory allocation, advanced bonding capacity and its own manufacturing yields.
The validation makes HBC harder to dismiss as a slide-deck architecture. It doesn’t yet establish a cheaper, faster or more efficient rack. The next evidence that matters is four-layer yield, measured power and thermal behavior, independently verified tokens per watt, and a customer deployment with volume attached. Until those arrive, the narrower AI250 sampling window is encouraging, but Qualcomm’s central claim remains unproven.
