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Feynman could make Nvidia A16’s first major customer

In sum – what we know:

• Skipping a generation – Nvidia’s Feynman GPUs are reportedly jumping from N3P straight to TSMC’s A16 node, bypassing the baseline N2 (2nm) generation entirely.
• A structural leap, not a shrink – A16 combines gate-all-around transistors with backside power delivery for the first time, which TSMC claims yields 8–10% higher speed or 15–20% lower power versus N2P.
• A multi-year runway – Risk production of A16 is targeted for 2026-2027, with Feynman mass production expected around 2028 and broad commercial rollout in 2029-2030.

Nvidia is reportedly designing its next-generation “Feynman” GPUs to debut on TSMC’s A16 node — a 1.6nm-class process — rather than the standard 2nm (N2) generation. Feynman is the successor to the Rubin and Rubin Ultra, which are on the 3nm-class N3P. If the reports hold up, Nvidia’s flagship AI silicon will effectively skip the baseline 2nm generation entirely, jumping straight from N3P-class designs to one of TSMC’s most advanced nodes.

That would also make Nvidia the first — and initially the only — major customer for A16, a position traditionally occupied by Apple. Apple, for its part, is expected to stick with baseline N2 for its 2026 iPhones. AMD and OpenAI are expected to become A16 customers eventually, but Nvidia reportedly holds early supply. That early access is strategically aimed at keeping a performance and efficiency lead over competing data center accelerators, most notably AMD’s MI-series.

To be clear, all of this stems from supply chain leaks — largely traced back to DigiTimes and Commercial Times — rather than anything Nvidia or TSMC have publicly confirmed beyond generic roadmap disclosures. Also, it’s currently unclear if Nvidia’s new chip will merely use A16 for some components, or for the whole design — but it will likely be the former.

Process technology

A16 is a structural transition, not a simple geometric shrink. That makes A16 qualitatively different from the incremental steps between N3 and N2. It’s the first TSMC node to combine gate-all-around (GAA) nanosheet transistors with backside power delivery, which TSMC brands as Super Power Rail. GAA replaces FinFETs with better electrostatic control and lower leakage, while backside power routes current through the back of the wafer instead of competing with signal wiring on the front.

Moving power rails to the backside reduces front-side routing congestion, voltage droop, and IR losses. For a chip the size of an Nvidia data center GPU, the freed-up front-side real estate translates into more cores, larger caches, and higher-bandwidth structures within the same physical footprint. Those are exactly the things that matter for AI and HPC workloads, where power delivery and interconnect congestion are chronic bottlenecks.

TSMC claims A16 delivers 8–10% higher speed at the same voltage compared to N2P, or 15–20% lower power consumption at the same performance level. Those are the manufacturer’s numbers, not independently verified ones — but even discounted somewhat, they help explain why Nvidia might prefer to wait for A16 rather than pour heavy investment into N2 for its largest chips. When your modules draw multiple kilowatts each, a 15–20% power reduction at iso-performance isn’t a rounding error.

Projected scale and performance

Feynman is aimed squarely at data center AI and HPC — this is not a consumer gaming architecture, at least not first. Individual modules are projected to consume multiple kilowatts each, continuing the trend already visible in Blackwell and Rubin systems, with compute capability estimated in the tens of petaFLOPS per module. Those figures are speculative projections, not formal specifications, and they should be read that way.

The hardware designs reportedly lean heavily on packaging. Feynman is expected to use 3D chiplets, stacking compute and cache tiles vertically, mixed with custom HBM stacks via 2.5D advanced packaging. Co-packaged optical interconnects are also expected to be integrated, giving GPU modules tightly coupled optical links for high-bandwidth, energy-efficient communication across server racks. 

The point of all this is cluster scale. Feynman platforms are positioned to support massive AI training fabrics well beyond today’s deployments, which is precisely the segment where AMD’s MI-series and the custom accelerators being built by large AI labs are trying to close the gap. Getting to A16 first is how Nvidia intends to keep that gap open.

Production timeline

TSMC originally planned to begin risk production of A16 in 2026, though some reports suggest that production has slipped to 2027. Mass production of Feynman silicon is broadly targeted for 2028, though some reports suggest early, limited deployments could happen in 2027 as manufacturing ramps. Broad commercial rollout and mass customer deliveries are expected around 2029–2030.

That’s a multi-year runway between risk production and volume shipments, which is normal for a node this ambitious — combining GAA and backside power in production for the first time is not a low-risk proposition. The exclusivity claims and the specific dates should both be treated as movable. If TSMC’s yields come in slower than hoped, or if other customers sign on earlier than expected, the timeline and Nvidia’s privileged position could shift accordingly. For now, though, the reported picture is a clear one — Nvidia, not Apple, driving the bleeding edge of TSMC’s roadmap, with Feynman as the payoff.