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The foundry has tapped substrate maker Kinsus to scale its silicon-bridge quasi-EMIB

In sum – what we know:

• A borrowed approach – TSMC’s internally-named “quasi-EMIB” embeds small silicon bridges in an organic substrate instead of using a full interposer, closely resembling Intel’s EMIB.
• Kinsus does the substrates – Taiwanese substrate maker Kinsus will design, test, and manufacture the advanced organic substrates that house the micro-bridges, mirroring Intel’s vertically integrated setup.
• A response to Nvidia – The project reads as a reaction to Nvidia evaluating Intel’s EMIB for its “Feynman” GPU platform, amid a 2026 CoWoS shortage with 52–78 week lead times.

TSMC is reportedly building its own answer to Intel’s EMIB. According to a recent report from The Information, the foundry is developing a packaging technology internally described as “quasi-EMIB” — a silicon-bridge approach designed to simplify manufacturing compared with CoWoS, cutting cycle times and packaging costs in the process. For a company that has spent years positioning CoWoS as the gold standard for AI accelerator packaging, borrowing a page from Intel’s playbook is a notable shift.

TSMC isn’t going it alone, either. The same reporting says the company is partnering with Kinsus Interconnect Technology, a major Taiwanese IC substrate supplier, to co-develop and scale the silicon-bridge package for large multi-die AI chips. Parallel reporting indicates Nvidia has been actively evaluating Intel’s EMIB for a future GPU platform, driven by the same bottlenecks TSMC is now scrambling to relieve. 

Who is Kinsus?

Kinsus Interconnect Technology is one of Taiwan’s major IC substrate makers, with a long track record in high-layer-count organic substrates used for CPUs, GPUs, and networking chips. According to the reporting, Kinsus will take primary responsibility for designing, testing, and manufacturing the advanced organic substrates that house the silicon micro-bridges at the heart of TSMC’s new package. That division of labor fits TSMC’s usual model — the foundry handles wafer-level integration and chip-on-wafer processes, while substrate partners take on the complex organic packages and back-end assembly.

Kinsus has reportedly been ramping investment in high-performance substrate manufacturing for some time, positioning it to support the large, high-power AI packages that come with tight routing density and demanding thermal constraints. That preparation matters here, because the substrates in a bridge-based package aren’t a commodity part — they’re where the bridges actually live.

The partnership also mirrors Intel’s own setup. Intel tightly couples EMIB with its internal packaging operations and substrate suppliers, and that vertical integration is part of why the technology has matured as quickly as it has. By bringing on a dedicated substrate ally, TSMC is effectively replicating that structure without building it all in-house.

TSMC’s quasi-EMIB vs Intel’s EMIB

The core idea behind both technologies is the same. Rather than placing dies on a large silicon interposer, small silicon bridges are embedded directly into an organic substrate, connecting adjacent dies with high-density, short-range interconnect. Intel has been shipping EMIB in volume for years across certain Xeon and accelerator families. TSMC’s version is much earlier-stage, with no product name, no disclosed timeline, and no confirmed lead customers as of late July.

The appeal for TSMC is straightforward. Full-size interposers in CoWoS-S limit how many units can be processed per wafer, and the first chip-on-wafer stage has become the major capacity choke point in the whole flow. By dropping the interposer in favor of embedded bridges, TSMC could raise effective units per wafer, improve yield, and ease that bottleneck — even if total capacity remains finite. It’s worth noting that CoWoS-L, TSMC’s newer variant, already moves in this direction by combining redistribution layers with local silicon bridges. The quasi-EMIB project appears to push further, embedding bridges in the substrate in a way that more directly resembles Intel’s structure.

That said, TSMC probably isn’t copying EMIB outright. Some analysts expect the company to blend EMIB-style bridges with CoWoS-like HBM integration — a hybrid tailored specifically to AI accelerators rather than a clone of Intel’s architecture. Whether it can match EMIB’s signal integrity and interconnect density while fitting into TSMC’s existing reliability and design-enablement framework is the open question, and one that won’t be answered until there’s actual silicon to evaluate.

Nvidia’s interest in Intel EMIB

The urgency behind TSMC’s project makes more sense in light of what Nvidia has been up to. Analysts have reported that Nvidia is evaluating Intel’s EMIB for a future GPU platform believed to be codenamed “Feynman,” driven by EMIB’s maturity, Intel’s aggressive packaging build-out, and a broader desire to reduce single-foundry risk as AI accelerator demand keeps outrunning TSMC’s capacity.

To be clear, this isn’t a migration. Nvidia would continue to rely heavily on TSMC for front-end wafer production and most of its packaging, with Intel EMIB serving as an exploratory supplement for selected configurations. And there’s no guarantee any of it happens — technical risk, ecosystem readiness, and customer acceptance will all determine how much of Nvidia’s portfolio can practically move to Intel packaging. Sources covering the evaluation have been careful to hedge on exactly those points.

But the mere prospect of Nvidia tapping Intel for packaging appears to have been a wake-up call. TSMC’s Kinsus partnership reads like a direct response — an attempt to give its biggest AI customers an EMIB-style option before they go looking for one elsewhere.

The 2026 packaging bottleneck

None of this happens without the shortage. Advanced packaging — CoWoS specifically — has become the primary constraint on AI accelerator production in 2026, often more binding than wafer fabrication itself. Lead times for AI-related packaging orders at TSMC are frequently cited in the 52–78 week range. Nvidia alone is believed to hold more than half of TSMC’s advanced CoWoS capacity through 2027, leaving everyone else to fight over the remainder.

Industry watchers track CoWoS running near or above 95%, and a sustained drop below 90% would be the first real signal that alternatives — whether Intel, Samsung, or panel-based OSAT processes — are meaningfully relieving the backlog. That hasn’t happened yet.

For TSMC, CoWoS dominance is a double-edged sword. It’s a strategic choke point that reinforces the company’s leverage over the AI supply chain, but it also breeds customer frustration and multi-sourcing efforts — exactly the dynamic the Nvidia-Intel reports illustrate. If the quasi-EMIB project succeeds, TSMC gets higher throughput, more flexible multi-die layouts, and lower per-package costs relative to CoWoS-S, while keeping customers in-house and holding its 2.5D/3D lead over Intel and Samsung. If it stalls, the EMIB advantage stays with Intel, and customer experimentation with Intel Foundry, Samsung, or panel-level packaging gets a lot more attractive.

Still, the caveats are worth keeping in mind. Design tools, IP blocks, and qualification flows for new bridge-based packaging take years to mature, and any gap between reported timelines and ecosystem readiness will slow actual adoption. There’s also the uncomfortable fact that TSMC and Kinsus are both Taiwan-based — the new packaging carries the same geopolitical exposure as the CoWoS lines it’s meant to relieve. TSMC may end up with a compelling answer to EMIB. It won’t be a quick one.