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Bigger CoWoS packages may keep AI accelerators scarce anyway
In sum – what we know:
- Doubled packaging capacity – TSMC could expand CoWoS from 130,000 to 260,000 wafers per month by the end of 2028.
- Bigger AI packages – A 14-reticle CoWoS option planned for 2028 supports 10 compute dies and 20 HBM stacks.
- Rival packaging pressure – Intel’s EMIB-T could reach 45,000 wafers monthly by 2028, still far below TSMC’s scale.
TSMC is reportedly preparing to roughly double capacity for its CoWoS advanced-packaging technology by the end of 2028. The estimate, according to analysts cited by Taiwan’s Economic Daily News, puts CoWoS capacity at about 130,000 wafers per month at the end of 2026, rising to about 260,000 per month two years later.
To be clear, none of this is confirmed TSMC guidance. The company has said publicly that it’s expanding CoWoS, but it hasn’t put the 130,000 or 260,000 figures on the record. Essentially, these are supply-chain estimates.
Regardless of whether the exact figures hold up, the direction is clear. TSMC’s AI-driven expansion is no longer confined to leading-edge wafer fabrication. Instead, it’s extending into the packaging stage that turns AI processors and high-bandwidth memory into finished, sellable accelerators.
What CoWoS is and why it matters
CoWoS stands for Chip on Wafer on Substrate. It’s TSMC’s 2.5D advanced-packaging platform, part of its 3DFabric portfolio, and it links high-performance logic dies — GPUs, AI accelerators, custom ASICs — with several stacks of high-bandwidth memory (HBM) using a silicon interposer and through-silicon vias. In plain terms, it’s the step that fuses a bare compute die and its memory into a single package. An advanced logic die coming off a 3nm or 2nm line isn’t a saleable AI accelerator until it has been packaged with HBM and tested, which is why CoWoS capacity has become a genuine bottleneck in the AI hardware supply chain.
The reason the technology matters so much comes down to memory. AI training and inference chips need far more memory bandwidth, and far more memory sitting physically close to the compute die, than conventional packages can efficiently provide. TSMC positions CoWoS as its answer for high-performance computing, supporting different interposer sizes, HBM counts, and package dimensions.
And those packages are getting big. TSMC is producing 5.5-reticle-size CoWoS — a reticle being the maximum area a lithography tool can expose in one pass. And, there’s a 14-reticle version planned for 2028. That larger package is designed to integrate roughly 10 large compute dies and 20 HBM stacks.
Plenty of demand
The immediate driver is sustained demand for AI data-center hardware, particularly accelerators that pair leading-edge compute dies with HBM. Nvidia is the most visible CoWoS customer, since its data-center GPUs rely on the technology, but AMD’s Instinct line and the custom-silicon programs at cloud providers pull from the same capacity pool. When Nvidia, AMD, and the hyperscalers are all competing for the same packaging slots, doubling capacity starts to look less like ambition and more like necessity.
TSMC itself has been fairly direct about the demand. At its April 2026 North America Technology Symposium, the company said AI customers need more computing power and more memory in a single package, and that it continues to expand CoWoS capabilities. Its official messaging has focused on the increasing size and integration level of those packages rather than on monthly output — which is partly why the analyst wafer figures are the only volume numbers circulating.
The tightness has also created openings for rivals. Intel’s EMIB-T is the notable alternative, using embedded bridges in an organic substrate rather than CoWoS’s silicon interposer. According to analysts cited by a Wccftech report, EMIB-T capacity, measured as 12-inch CoWoS-equivalent wafers, could reach 15,000 to 20,000 wafers per month in 2027 and 40,000 to 45,000 in 2028. The same reporting suggests EMIB-T could be most relevant to custom accelerators from cloud companies like Google and Amazon, though no customer commitments are confirmed. Even at the high end of those estimates, Intel would be running at a fraction of TSMC’s reported scale.
Where the added capacity would be built
According to the analyst reports, the incremental capacity would be centered on TSMC’s AP7 advanced-packaging site in Chiayi, Taiwan, and on the company’s Arizona campus. Near term, though, U.S. packaging runs mainly through TSMC’s 10-year agreement with Amkor. A packaging plant built by TSMC itself in Arizona is targeted for around 2029. Taiwan remains TSMC’s primary advanced-packaging base. But, a larger U.S. packaging footprint would eliminate the need to ship U.S.-made advanced chips back to Taiwan for final packaging — a logistical round trip that undercuts some of the point of fabricating in Arizona in the first place.
For American AI-chip customers, that would shorten logistics chains and chip away at one of the more glaring geographic concentration risks in the semiconductor supply chain. But the specific Arizona CoWoS timetable and plant allocations come from secondary supply-chain reporting, not from TSMC. Treat them accordingly.
Why doubled capacity may not fully resolve shortages
Doubling capacity over two years would be a large response by any measure. But demand for AI compute and HBM-equipped packages may keep rising over the same period, and packaging doesn’t exist in isolation. It depends on other constrained inputs — HBM supply, substrates, interposers, specialized tools, testing capacity, and engineering labor. Any one of those can become the new bottleneck once wafer-equivalent capacity stops being the limiting factor.
There’s also a subtler math problem. Larger packages consume more resources per processor, and the 14-reticle CoWoS coming in 2028 will consume dramatically more interposer area and HBM per unit than today’s packages. A doubling of wafer-equivalent capacity, in other words, does not translate into a doubling of finished AI accelerators. The effective gain in shipped units could be considerably smaller.
And demand itself carries risk. AI spending is volatile and concentrated among a handful of major customers. A slowdown in hyperscaler capital spending, a shift in AI-chip architectures, or successful diversification toward Intel’s EMIB-T or outsourced packaging providers like ASE and Amkor could all change the economics of an aggressive build-out. Overseas expansion adds its own cost, staffing, and coordination challenges relative to Taiwan-based operations. The open question is whether even a doubled footprint can keep pace with packages that are growing faster than the capacity built to produce them.
