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In production now, but 2nm’s first prize for AI is efficiency

TSMC has begun scaling its first 2nm-class process after entering volume production late last year, turning the shift from FinFET to nanosheet transistors into a commercial reality. N2, as TSMC calls it, is the company’s first production node built around gate-all-around (GAA) transistors — a fundamental change in how the gate controls current through the channel, replacing the FinFET architecture that carried the industry through 3nm.

For AI, the immediate payoff probably isn’t a dramatic leap in raw model performance. It’s efficiency. TSMC targets significant power and performance improvements over its preceding N3E process, and for an industry where electricity and cooling costs rival the cost of the silicon itself, that tradeoff matters enormously. How quickly the benefit reaches actual AI hardware will depend on more than wafer lithography, though. Packaging capacity, HBM memory supply, yield maturity, and customer access to scarce leading-edge capacity all determine the pace. And TSMC isn’t the only foundry making the GAA transition. Samsung and Intel are running their own timelines.

The state of the 2nm ramp

TSMC says N2 entered volume production in Q4 2025, on schedule. The company’s Q2 2026 management report puts 2nm at 3% of total wafer revenue, up from effectively zero the prior quarter. That confirms the ramp has started commercially. It also shows how early things still are. In the same quarter, 3nm represented 30% of wafer revenue and 5nm accounted for 33% of wafer revenue. The new node is generating revenue, but it remains a sliver of TSMC’s overall output.

That trajectory is fairly normal for a leading-edge process. New nodes start small, carry premium pricing, and scale as yields improve and customer designs reach production. TSMC has said demand for its leading-edge technologies is being supported by HPC and AI applications, and Reuters reported the company expects strong multi-year AI demand as it expands capacity, including its U.S. footprint.

Worth noting is the fact that “2nm” is a commercial process-node name, not a literal measurement of any transistor feature. It signals a new generation of manufacturing technology, density improvements, and power-performance tradeoffs. Samsung and Intel use their own branded labels for competing processes, and none of these designations map directly to an actual physical dimension. Samsung calls its node “2nm,” Intel uses “18A.” Comparing across them requires care, since each company uses different design rules, transistor configurations, and performance targets.

Samsung began its own 2nm-class production effort in 2025 and is working to improve yields and build customer volume. Intel’s 18A is positioned as a leading-edge alternative for both Intel’s own products and prospective foundry customers. All three foundries now build on GAA transistors, though Samsung got there first, at 3nm in 2022. The node labels still aren’t apples-to-apples.

The early AI story here is about efficiency rather than speed. TSMC’s process-level targets for N2 promise meaningful power and performance gains over N3E — enough to shift the economics for AI infrastructure where power draw is a defining constraint. Those are benchmarks under controlled conditions, not guaranteed product outcomes, and actual chip-level improvements will vary by design, workload, and a host of other factors. But even partial realization of those gains changes the math for data center operators.

Where production is happening and what’s next

TSMC’s first N2 manufacturing sites are Fab 20 in Hsinchu/Baoshan and Fab 22 in Kaohsiung, both in Taiwan. The company’s Arizona expansion is part of the broader capacity story — TSMC produced the first Blackwell wafer for Nvidia at its Arizona facility on an older process, underscoring U.S. ambitions. That wafer still ships back to Taiwan for advanced packaging. But the initial 2nm ramp is centered in Taiwan. U.S.-based N2 output isn’t yet supplying the market.

Reports citing supply-chain sources have put potential end-of-2026 N2 capacity at roughly 100,000 to 120,000 wafers per month. TSMC hasn’t publicly confirmed a specific monthly target, so those figures should be treated as informed estimates rather than official guidance. Either way, the scaling through 2026 will be gradual. Leading-edge ramps always are.

The roadmap beyond base N2 is already defined. N2P, an enhanced variant with further performance and power improvements, is scheduled for volume production in the second half of 2026. It’s an evolutionary step on the same nanosheet GAA foundation — refinement, not reinvention.

TSMC is also preparing A16, which is production-ready in 2026 with volume production guided to 2027. A16 is related to the N2 family but technically distinct. It combines nanosheet transistors with backside power delivery, a technique that routes power connections through the back of the silicon die rather than competing for space on the front side with signal wires. That’s designed to address power-delivery and routing constraints that become particularly acute in very large, high-current chips — exactly the kind built for AI and HPC. Intel’s 18A already incorporates backside power delivery, which gives it a structural differentiator against TSMC’s N2 and N2P. TSMC doesn’t match that specific capability until A16 reaches production.

For customers, the multi-foundry dimension matters. Major AI companies increasingly want supply-chain resilience, and Samsung’s 2nm ramp and Intel’s 18A ambitions give them options — even if TSMC remains the dominant supplier of advanced logic by a wide margin. The ability to qualify designs across more than one foundry has become a strategic priority for hyperscalers investing billions in AI infrastructure.

How 2nm changes the transistor playbook

N2’s defining architectural shift is the move from FinFET to nanosheet GAA transistors. In a FinFET, the gate wraps around a vertical fin on three sides to control current flow. In a GAA design, the gate wraps around stacked horizontal nanosheets, surrounding the channel more completely. The result is stronger electrostatic control, which reduces leakage and gives chip designers more flexibility to tune for speed or efficiency depending on the application.

Reduced leakage translates directly into lower static power consumption. Better gate control means designers can push transistors harder within a given thermal budget, or conversely, pull back voltage and achieve the same performance with less heat. TSMC’s N2 targets reflect that flexibility. The company projects 15% higher performance at the same power, or 30% lower power at the same performance, versus N3E — figures it restated at IEDM 2024. It also claims more than 15% higher chip density, though actual chip-level improvements will depend heavily on the SRAM/cache mix, frequency targets, library choices, and packaging decisions for any given design.

Beyond the transistor itself, TSMC says N2 incorporates low-resistance redistribution layers and high-performance metal-insulator-metal (MIM) capacitors to improve power delivery and circuit performance. N2P extends these improvements when it arrives in the second half of 2026, building on the same architectural foundation without fundamental changes.

Samsung’s 2nm process also uses GAA transistors, though with different design rules and routing choices that will shape real-world performance differently depending on the workload. Intel’s 18A takes a related approach to the transistor structure but pairs it with backside power delivery from the outset. For AI and HPC designs that push enormous current densities, backside power delivery can meaningfully reduce voltage droop and improve routing efficiency. It’s a real differentiator for Intel, at least until TSMC’s A16 reaches volume production and levels that part of the playing field.

What 2nm brings to AI

AI’s limiting factor at data center scale is increasingly energy, cooling, and power delivery. Training runs and inference workloads demand enormous compute, and the electricity required to power and cool that compute has become one of the largest cost drivers in modern AI infrastructure. A lower-power process node gives chip designers room to move. They can run a design at similar performance while drawing less energy. They can pack in more compute or raise frequencies within a fixed power envelope. They can reduce heat density and ease cooling demands. Or they can reallocate part of a power budget toward memory interfaces, interconnects, and caches.

Nvidia’s Blackwell GPUs are built on TSMC’s custom 4NP process. AMD’s MI300X uses a mix of 5nm and 6nm. When accelerators of that caliber eventually move to 2nm-class processes, the efficiency gains compound across tens of thousands of servers. If TSMC’s targets are even partially realized at the product level, a 20–30% power improvement at comparable performance translates directly into lower operating costs and potentially more compute per rack. The most visible benefit may not show up as a faster model. More likely, it appears as better performance per watt, higher utilization, or reduced total cost of ownership.

TSMC’s own revenue mix illustrates why the company’s roadmap is discussed through an AI lens. In Q2 2026, HPC accounted for 66% of revenue, versus 22% for smartphones. Not all of that HPC revenue is AI, and not all AI chips will move to N2 right away. But the directional shift is clear.

Density improvements at the 2nm node help designers fit more logic or cache onto a die, though the process alone doesn’t eliminate the need for advanced packaging and high-bandwidth memory. Modern AI accelerators are systems assembled from logic dies, HBM stacks, interposers, and complex packaging. AI throughput can remain constrained even as N2 wafer capacity expands, because CoWoS-class advanced packaging and HBM supply are entirely separate bottlenecks.

At the edge, the power advantage may matter even more than raw performance. Phones, laptops, cars, and industrial devices all operate within tight thermal and battery constraints. Compared with N3E-era silicon, 2nm-based NPUs and AI accelerators should handle more on-device inference without degrading battery life or requiring active cooling. Qualcomm, Apple, and MediaTek are all widely expected to be among the early adopters of N2 for mobile application processors, and the AI capabilities in those chips are a major reason why.

Why not all AI will jump to 2nm immediately

The largest AI accelerators don’t automatically adopt the newest process node first. Product schedules, design complexity, yield maturity, die size, packaging availability, memory supply, and economics all shape the timing. N2 wafers carry a substantial premium over older nodes, and the math works more easily for high-margin smartphone application processors and large-scale AI infrastructure than for every chip category.

There’s also a question of where the real performance bottleneck actually sits. Memory bandwidth, HBM generation, chip-to-chip interconnect speed, packaging yield, system architecture, and software utilization can all have as much impact on real-world AI throughput as the transistor node. A chip on a mature 5nm process paired with optimized advanced packaging and the latest HBM could outperform a first-generation N2 design still working through early yield curves — and cost less per unit of compute in the process.

Some companies have been making this tradeoff deliberately. Earlier versions of Google’s TPUs and Meta’s MTIA were built on 7nm. Newer iterations moved to 5nm, sidestepping the scramble for cutting-edge capacity while meeting their performance targets. Custom ASICs have particular flexibility here, since they’re designed for specific workloads rather than general-purpose performance, and they can match the process node to the job.

The move to 2nm should be understood as a multi-year platform shift, not a single event. The first wave will prioritize designs where the power and density benefits justify the cost and yield risk. Broader adoption follows as N2 and its variants mature, wafer pricing normalizes, and the supporting ecosystem — packaging, memory, design tools — catches up.

How rivals stack up

TSMC isn’t the only foundry making the GAA transition, and its competitors’ progress matters precisely because major AI customers want credible alternatives.

Samsung has been ramping its 2nm-class production and working to attract customers, but the challenge goes well beyond having GAA transistors in production. Yield maturity, IP library availability, and manufacturing consistency across wafer lots all factor into customer decisions. Samsung has historically struggled to close the gap with TSMC on those dimensions. Whether its 2nm process becomes a genuine high-volume alternative for AI and mobile chips, or remains a secondary option, depends on execution over the coming quarters.

Intel’s 18A presents a different competitive dynamic. Backside power delivery is a technical differentiator against TSMC’s base N2 and N2P, and Intel is investing heavily in its foundry ambitions. Whether that translates into meaningful external customer wins is still an open question. Intel’s packaging capabilities, foundry service maturity, and ability to pry designs away from companies with deep TSMC relationships are all works in progress. Building a foundry business against an entrenched incumbent with decades of ecosystem momentum takes time, regardless of how strong the underlying transistor technology is.

TSMC’s competitive position rests on more than any single process node. Manufacturing scale, long-standing customer relationships, a mature EDA ecosystem, advanced packaging leadership, and the ability to ramp multiple generations of leading-edge technology simultaneously — those advantages compound over time and are difficult to replicate quickly. Competitors don’t need to match TSMC on every front to be relevant, though. Being good enough on enough dimensions to serve as a credible second source has real value, especially as supply-chain concentration becomes its own risk factor for hyperscalers.