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CUBE bets on 3D stacking and custom HBM for AI accelerators

In sum – what we know:

• 3D stacking strategy – CUBE pushes vertical die expansion, co-layout and bandwidth gains over larger board footprints.
• HBM4 production momentum – Samsung shipped HBM4 first, topping $1 billion in sales with yields near 80%.
• Custom HBM expansion – Samsung is growing ASIC share, tripling HBM sales and pursuing long-term supply deals.

Samsung has announced what it’s calling the CUBE strategy, a long-term roadmap for rethinking how AI memory chips are built — covering 3D stacking, bandwidth scaling, and power and thermal efficiency. CUBE stands for Capacity, Utilization, Bandwidth, and Efficiency, and Samsung frames it less as a product line and more as a development methodology that will guide its future DRAM and HBM architectures.

Massive LLM and AI training demand has reshaped the memory market over the past few years, and Samsung has watched SK Hynix take the lead in deployed high-bandwidth memory while Micron gains ground of its own. CUBE is Samsung’s attempt to protect what market share it has left in AI memory and rebuild the rest.

Technical vision and core pillars

The core technical idea behind CUBE is that memory capacity gains should come from vertical die expansion rather than a larger printed circuit board footprint. Samsung has said it will “no longer be limited by PCB area,” scaling capacity through stacking and advanced packaging instead. That matters for AI servers, where board space and power envelopes are already stretched thin — more memory per square millimeter means denser accelerator configurations without redesigning the rack.

Stacking higher is only part of it, though. Samsung argues that the industry has mostly just piled chips on top of each other, and that further gains now require structural changes — shorter physical distances between memory dies, and logic and memory laid out together rather than designed in isolation. The goal is to cut latency and improve effective bandwidth, with 3D architectures adding parallel data channels while keeping signal integrity under control. Underneath all of it sits a single design metric Samsung keeps returning to — the energy required to move one bit of data. For hyperscalers watching data center power bills climb, that’s arguably the pillar that matters most.

Where SK Hynix has won by executing quickly on successive HBM generations, Samsung is betting that packaging and structural innovation will matter more alongside execution in the next phase.

The technical hurdles are worth noting, too. Pushing 3D stacking further introduces yield, reliability, and thermal management problems that get notoriously harder to test as stack heights grow. And logic-memory co-layout isn’t something Samsung can do alone. It requires close cooperation with CPU, GPU, and ASIC vendors, all of whom have their own design preferences and their own timelines. Nvidia and the major ASIC designers won’t reshape their architectures around Samsung’s vision unless the numbers clearly justify it.

Product roadmap and next-generation memory

The roadmap under CUBE starts with HBM4, which Samsung moved into mass production in February 2026 using tightly integrated Design Technology Co-Optimization (DTCO) between its logic and memory units. That internal restructuring is worth noting — Samsung is one of the few memory makers with a logic foundry under the same roof, and CUBE’s co-layout ambitions lean heavily on that. Samsung later reported HBM4 surpassed $1 billion in sales within about 130 days and reached ~80% yield within about six months of mass production.

Further out, HBM5 — the eighth generation of high-bandwidth memory — is in development, with Samsung explicitly targeting double the performance of HBM4E, samples of which began shipping in May. The company is also preparing zHBM, a next-generation 3D memory built around vertical z-axis innovations, which Samsung claims can reduce thermal resistance by up to 90%. If that figure turns out to be correct, it would be significant for the very high-stack configurations used in AI GPUs and ASICs, where heat is the binding constraint. Alongside zHBM, Samsung is developing zNAND-O, a hybrid memory sitting somewhere between NAND and DRAM concepts, aimed at LLM workloads that need high capacity with lower latency than conventional flash.

On the conventional DRAM side, Samsung is transitioning to sixth-generation 10nm (1c) DRAM. These migrations are less flashy than zHBM, but they underpin the Capacity and Efficiency pillars — denser, lower-power DRAM is what feeds the stacked and packaged products above it.

The pressure point is timing. SK Hynix’s HBM sits in more deployed AI accelerators than anyone else’s right now, and memory design wins tend to stick — once a GPU or ASIC generation qualifies a supplier, switching is painful. If HBM5 or zHBM slips out of alignment with the next accelerator generations, customers will simply lock into competing memory ecosystems, and Samsung will be playing catch-up for another cycle.

Business strategy and supply dynamics

Samsung expects its HBM sales to more than triple in 2026 to meet AI data center demand that remains, by the company’s own account, constrained. That’s an enormous capacity commitment, and Samsung wants more certainty behind it. The company is considering a shift from typical quarterly memory agreements to three- to five-year contracts with major customers — a structure meant to stabilize supply planning, reassure AI chipmakers and cloud firms worried about shortages, and reduce the volatility in Samsung’s own investment decisions.

There’s also a deliberate move to broaden the customer base. Samsung is aiming to allocate a growing share of its HBM output to ASIC clients in 2026, expanding its ASIC customer base beyond the traditional GPU vendors and hyperscalers that have dominated HBM demand so far.

Compared to SK Hynix and Micron, Samsung’s positioning here is explicitly about margin resilience. Premium, customized HBM products hold their value better than commodity DRAM when prices soften, and Samsung has been through enough memory cycles to know a downturn always arrives eventually.

That said, the risks cut both ways. If AI demand normalizes or slows, sharply expanded HBM capacity becomes overcapacity, and the price pressure that follows would undermine the returns on every CUBE-driven investment. Long-term contracts are a double-edged sword too. They stabilize revenue, but they could lock Samsung into pricing that looks distinctly unfavorable if technology or market conditions shift faster than a five-year agreement anticipates. In a market moving this quickly, that’s not a hypothetical.

National positioning and the super-gap strategy

Samsung positions CUBE as a way to maintain a “super-gap” in memory technology — a lead wide enough that its chips become the default choice for AI servers and edge accelerators rather than one option among several. The strategy dovetails with South Korea’s governmental push to support advanced semiconductor investment and preserve the country’s status as a memory powerhouse, and the domestic stakes are treated as national ones.

The concern driving that framing is twofold. Chinese memory makers are scaling up alongside domestic Chinese AI hardware projects, and while they aren’t competitive at the leading edge today, the trajectory is clear enough that Korea’s industry sees CUBE partly as a technology defense. Against Micron, the play is different — rather than competing on price with Micron’s expanding advanced DRAM lineup, Samsung is pushing customized HBM stacks, advanced packaging, and co-design, betting that deep integration with customers’ silicon is harder to displace than a cheaper part.