Table of Contents
Verkor autonomously generated a layout-ready RISC-V core from a short requirements document
In sum – what we know:
- Rapid autonomous cycles – Verkor’s Design Conductor system transformed a 219-word requirements document into a layout-ready GDSII file in 12 hours without human intervention.
- Simulation vs. reality – The resulting VerCore CPU has been verified through the Spike simulator and academic PDKs, but it has not yet been physically fabricated or tested on silicon.
- Human-dependent precision – Despite the autonomous branding, the system requires highly engineered input specifications and an estimated 5 to 10 experts to steer the output toward production-grade quality.
Chip design startup Verkor.io has made a pretty bold claim — that its agentic AI system, called Design Conductor, has autonomously designed a complete RISC-V CPU core in 12 hours flat. The design started from a 219-word requirements document, and the system created a verified, layout-ready GDSII file with zero human intervention during the actual design process. Verkor describes the speedup as “orders of magnitude” faster than the industry norm.
There’s a research paper backing the claims, published in March 2026, and VerCore is being positioned as the first complete RISC-V CPU core designed end-to-end by an AI agent. The important caveat here, though, is that the chip hasn’t actually been physically fabricated.
Tech specs
Under the hood, VerCore runs a 5-stage pipelined architecture with single-issue, in-order execution. It supports the RV32I and ZMMUL instruction sets, though compressed instruction support is missing. You get 32-bit instruction interfaces, with the whole thing configured as a synchronous design using a clock input and reset input.
Performance-wise, VerCore clocked in at 1.48 GHz — just shy of the 1.6 GHz target — and posted a CoreMark score of 3,261. For context, that puts it roughly in the same neighborhood as a mid-2011 Intel Celeron SU2300. Nobody’s going to confuse this with cutting-edge silicon. But for a design that was produced in half a day without a human touching the wheel, it’s a genuinely interesting data point. Verkor says VerCore hits a Cycles Per Instruction target of 1.5 or below, and claims the design can run a uCLinux variant in simulation.
Design Conductor workflow
The way Design Conductor works is by orchestrating large language models through a structured sequence of steps that essentially mirrors how human engineers approach chip design — moving from RTL specification all the way through to layout generation. Everything is produced autonomously, and the system stays compatible with existing Electronic Design Automation tools. That matters because it means Design Conductor plugs into the standard toolchains chip designers are already using, rather than requiring an entirely new workflow.
That said, the system only works well when the input spec is written in what Verkor calls an “extremely deliberate, tight, and verifiable/measurable manner.” That 219-word spec that kicked off VerCore wasn’t some casually tossed-off prompt. It was a carefully engineered requirements document. So the output quality, as is often the case with AI systems, remains deeply tied to the precision and quality of what goes in.
Verification
VerCore hasn’t been physically fabricated yet. All verification has happened in simulation, using the Spike reference simulator (a standard RISC-V ISA tool) and an academic ASAP7 process design kit rather than a production node. The distance between a simulated design running on an academic PDK and a chip that actually functions on real silicon is enormous, and no AI-designed chip has managed to cross that gap yet.
Verkor’s own researchers have been fairly candid about where the system struggles. They acknowledge that Design Conductor can underestimate the complexity of certain design challenges and occasionally gets stuck in debugging loops that a seasoned human engineer would navigate around easily. One particularly revealing example is that when the system couldn’t meet timing requirements, it went for a major pipeline deepening instead of applying simpler, more surgical fixes. The system also has a tendency to reason about event-driven hardware description languages as if they were sequential code, which represents a pretty fundamental conceptual mismatch.
Scaling is another concern. Compute requirements grow non-linearly as design complexity increases, which creates real practical ceilings on how far the system can be pushed. And despite all the “autonomous” framing, Verkor estimates that 5 to 10 human experts are still needed to steer the system toward anything production-ready. That’s a meaningful qualifier on any claim of full autonomy.
The future of chip design?
Verkor’s work does stand apart from earlier AI-assisted chip design efforts in some notable ways. The 2023 QiMeng project from Chinese researchers produced a RISC-V CPU in under five hours, but took a different methodological approach. What Design Conductor claims as its differentiator is handling the entire pipeline from specification to GDSII autonomously, rather than just automating individual pieces of the workflow. That said, no AI-designed chips — VerCore included — have made it to physical silicon yet.
It’s also worth noting that a chip like VerCore is typically a one- or two-person project in a commercial setting. The real test for a system like Design Conductor isn’t whether it can produce a modest in-order RISC-V core — it’s whether it can scale to the kind of complex, multi-billion-transistor designs that represent the actual bottleneck in the semiconductor industry.
On the roadmap side, Verkor plans to open-source VerCore’s RTL source code and build scripts by the end of April 2026, which should give the broader community a chance to dig into the design properly. An FPGA implementation is set to be showcased at the upcoming Design Automation Conference. Longer term, Verkor is aiming to partner with fabless companies to deploy Design Conductor as a time-to-market accelerator. That’s an ambitious target, and whether it pans out will ultimately hinge on whether the system can prove itself on designs far more complex than VerCore.
